Name :
Dr. S Rao Chintalapudi Subject : Compiler Design
Designation :
Associate Professor Subject
Code : 16CS5T09
Department :
CSE Year & Semester : III-I Sem
LESSON PLAN
S.No.
|
Topic
|
Mode of Delivery
|
No. of Classes
(Lecture No.)
|
Suggested Books
|
|
UNIT-I: Overview of Language Processing
and Lexical Analysis
|
|||||
1
|
Introduction to language processing
|
Board
& Chalk
|
L1
|
T1-CH1
R1-CH1
|
|
2
|
Preprocessors, Compilers,
|
Board
& Chalk
|
L2
|
T1-CH1
R1-CH1
|
|
3
|
Assembler, interpreters
|
Board
& Chalk
|
L3
|
T1-CH1
R1-CH1
|
|
4
|
Linkers & loaders
|
Board
& Chalk
|
L4
|
T1-CH1
R1-CH1
|
|
5
|
Structure of a compiler
|
Board
& Chalk
|
L5
|
T1-CH1
R1-CH1
|
|
6
|
Phases of a compiler
|
PPT
|
L6
|
T1-CH1
R1-CH1
|
|
7
|
Lexical Analysis – Role of Lexical
Analysis
|
Board
& Chalk
|
L7
|
T1-CH3
R1-CH1
|
|
8
|
Input Buffering
|
PPT
|
L8
|
T1-CH3
R1-CH1
|
|
9
|
specification of lexemes, tokens
|
PPT
|
L9
|
T1-CH3
R1-CH1
|
|
10
|
Recognitions of tokens
|
Board
& Chalk
|
L10
|
T1-CH3
R1-CH1
|
|
11
|
Transition diagrams
|
PPT
|
L11
|
T1-CH3
R1-CH1
|
|
12
|
lexical
analyzer generator tool-Lex
|
PPT
|
L12
|
T1-CH3
R1-CH1
|
|
UNIT-II : Syntax Analysis
|
|||||
13
|
Syntax Analysis: The role of a parser
|
Board
& Chalk
|
L13
|
T1-CH4
R1-CH2
|
|
14
|
Context Free
Grammars(CFG)s
|
Board
& Chalk
|
L14
|
T1-CH4
R1-CH2
|
|
15
|
LMD, RMD,
Parse Trees
|
PPT
|
L15
|
T1-CH4
R1-CH2
|
|
16
|
classification
of parsing techniques
|
Board
& Chalk
|
L16
|
T1-CH4
R1-CH2
|
|
17
|
Topdown
parsing
|
PPT
|
L17
|
T1-CH4
R1-CH2
|
|
18
|
Recursive descent parsing
|
Board
& Chalk
|
L18,L19
|
T1-CH4
R1-CH2
|
|
19
|
LL(1) parsing
|
Board
& Chalk
|
L20,L21
|
T1-CH4
R1-CH2
|
|
20
|
Error recovery
in predictive parsing.
|
PPT
|
L22,L23
|
T1-CH4
R1-CH2
|
|
UNIT-III : Bottom up parsing
|
|||||
21
|
Bottom up parsing: Shift Reduce Parsing
|
Board
& Chalk
|
L25
|
T1-CH4
R1-CH3
|
|
22
|
Introduction to LR Parser, Model of an LR Parsers
|
Board
& Chalk
|
L26
|
T1-CH4
R1-CH3
|
|
23
|
SLR parsing
|
Board
& Chalk
|
L27,L28
|
T1-CH4
R1-CH3
|
|
24
|
More Powerful LR parsers: CLR
|
Board
& Chalk
|
L29,L30
|
T1-CH4
R1-CH3
|
|
25
|
LALR parsers
|
Board
& Chalk
|
L31,L32
|
T1-CH4
R1-CH3
|
|
26
|
Error Recovery in LR parsing
|
PPT
|
L33,l34
|
T1-CH4
R1-CH3
|
|
27
|
YACC tool
|
PPT
|
L35
|
T1-CH4
R1-CH3
|
|
UNIT-IV : Semantic Analysis and intermediate code generation
|
|||||
28
|
Semantic Analysis: Syntax Directed
Definition
|
Board
& Chalk
|
L36
|
T1-CH5
R1-CH4
|
|
29
|
Synthesized Attributes &Inherited
attributes
|
Board
& Chalk
|
L37
|
T1-CH5
R1-CH4
|
|
30
|
Evolution order of SDDs
|
Board
& Chalk
|
L38
|
T1-CH5
R1-CH4
|
|
31
|
Intermediate Code Generation: Variants of
Syntax trees
|
PPT
|
L39
|
T1-CH6
R1-CH4
|
|
32
|
DAGs
|
PPT
|
L40
|
T1-CH6
R1-CH4
|
|
33
|
Three Address code, Quadruples, Triples, Indirect
Triples
|
PPT
|
L41,L42
|
T1-CH6
R1-CH4
|
|
34
|
Types and Declarations
|
Board
& Chalk
|
L43
|
T1-CH6
R1-CH4
|
|
35
|
Type Checking
|
Board
& Chalk
|
L44
|
T1-CH6
R1-CH4
|
|
UNIT-V : Symbol Tables and Code generation
|
|||||
36
|
Symbol tables: Need of Symbol tables
|
Board
& Chalk
|
L45
|
T1-CH1,CH2
R1-CH1
|
|
37
|
Runtime Environments
|
PPT
|
L46
|
T1-CH7
R1-CH6
|
|
38
|
Stack allocation of space
|
Board
& Chalk
|
L47
|
T1-CH7
R1-CH6
|
|
39
|
Access to non-local data
|
Board
& Chalk
|
L48
|
T1-CH7
R1-CH6
|
|
40
|
Heap Management
|
PPT
|
L49
|
T1-CH7
R1-CH6
|
|
41
|
Code generation: Issues in design of code
generation
|
Board
& Chalk
|
L50
|
T1-CH8
R1-CH7
|
|
42
|
The target Language, Basic blocks and
Flow graphs
|
PPT
|
L51
|
T1-CH8
R1-CH7
|
|
43
|
Basic blocks & flow graphs
|
PPT
|
L52
|
T1-CH8
R1-CH7
|
|
44
|
Simple code generator, Peephole
optimization
|
Board
& Chalk
|
L53
|
T1-CH8
|
|
UNIT-VI : Machine Independent Code Optimization
|
|||||
45
|
Machine Independent Code Optimization:
The principle sources of Optimization
|
Board
& Chalk
|
L54
|
T1-CH9
R1-CH8
|
|
46
|
Global common sub expression elimination
|
PPT
|
L55,L56
|
T1-CH9
R1-CH8
|
|
47
|
Copy propagation, dead code elimination
|
PPT
|
L57,L58
|
T1-CH9
R1-CH8
|
|
48
|
Constant folding, strength reduction
|
PPT
|
L59,L60
|
T1-CH9
R1-CH8
|
|
49
|
Loop optimization, Instruction scheduling
|
Board
& Chalk
|
L61,L62
|
T1-CH9
R1-CH8
|
|
Total number of hours = 62
TEXT BOOKS:
1. “Compilers, Principles Techniques and Tools,” Alfred V Aho, Monical S. Lam, Ravi SethiJeffery D. Ullman,2nd edition,Pearson,2007.
2. “Compiler Design,” K.Muneeswaran, OXFORD, 2012.
1. “Compilers, Principles Techniques and Tools,” Alfred V Aho, Monical S. Lam, Ravi SethiJeffery D. Ullman,2nd edition,Pearson,2007.
2. “Compiler Design,” K.Muneeswaran, OXFORD, 2012.
REFERENCE BOOKS:
1.“Principles of compiler design,” Nandhini Prasad, Elsevier, 2ndedition, 2012.
2.“Compiler Construction, Principles and practice,”Kenneth C Louden,CENGAGE, first edition 2006.
3.“Implementations of Compiler,A New approach to Compilers including the algebraicmethods,” Yunlinsu,SPRINGER, 2011.
1.“Principles of compiler design,” Nandhini Prasad, Elsevier, 2ndedition, 2012.
2.“Compiler Construction, Principles and practice,”Kenneth C Louden,CENGAGE, first edition 2006.
3.“Implementations of Compiler,A New approach to Compilers including the algebraicmethods,” Yunlinsu,SPRINGER, 2011.
WEB RESOURCES:
(Signature of the Faculty) (Signature of the HOD)
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